What you'll do: • Design, implement, and verify RTL logic in Verilog or SystemVerilog targeting ultra-low-latency trading applications • Develop simulation testbenches and functional verification environments to validate FPGA designs before hardware deployment • Work closely with senior FPGA engineers and the trading infrastructure team to understand latency requirements and translate them into hardware design decisions • Run synthesis, place-and-route, and static timing analysis; iterate on designs to meet strict timing constraints • Participate in hardware bring-up and on-board debugging, using waveform analysis and other diagnostic tools • Use AI tools to accelerate your development …
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