Join our hardware team as an intern or co-op verifying the accelerator, with hands-on ownership of verification environments from test plan through coverage closure and bring-up. Get hands-on exposure to chip design and verification — perfect for EE/CompE students curious about how it all comes together. What you'll do • Work with your mentor to develop verification plans for the accelerator • Write and debug SystemVerilog/UVM testbenches, checkers, and stimulus for your assigned block • Build tests, scoreboards, and reference models, and close functional and code coverage • Triage and root-cause failures with RTL designers, with mentorship from senior engineers • Participate in …
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The rest of the description, the direct apply link, your match score, a tailored resume and the recruiters to message all come with internOS Pro. 3 days free, then $10/month. Cancel anytime.